Fabian Schuiki

As the pioneering force behind RISC-V, SiFive continues to lead the charge in innovation and efficiency within computing.

As part of my work at SiFive, I develop novel compiler IR dialects for the CIRCT open-source project. Together with a vibrant community of collaborators from SiFive, academia, and the open-source world at large, we are building the foundation for the next generation of hardware design tools.

My contributions include:

• A SystemVerilog frontend based on the Slang project, which combines my prior work on LLHD and the Moore compiler into a robust and reusable set of MLIR dialects and lowering passes. Based on this work, SiFive is able to compile industry-grade Verilog IP with CIRCT and use it alongside the existing Chisel-based workflow.

• A fast simulator for hardware designs, based on the restructuring of the input design into register-to-register transfer arcs. These arcs allow for very aggressive optimizations to be performed, such as stratifying simulation execution on clock edges. And by leveraging MLIR’s tight integration with LLVM, the simulator can generate very fast native machine code to execute the simulation.

• Verification dialects aiming to capture assertions, assumptions, and coverage of boolean and temporal properties. These dialects allow CIRCT to represent SystemVerilog assertions, give Chisel an opportunity to emit temporal properties, and enable CIRCT-based formal verification tools.

• A debug dialect to capture source-language debugging information and carry it through the compiler pipeline as part of the IR. This has allowed us to demonstrate Chisel-level debugging of hardware designs in a collaboration with Synopsys. Furthermore, debug information can be used to translate Verilog-level waveforms back to the source language.

Established in 1854 with the stated mission to educate engineers and scientists, the school focuses exclusively on science, technology, engineering, and mathematics. More than twenty Nobel laureates, including Albert Einstein, have either studied at ETH or were awarded the Nobel Prize for their work achieved at ETH.

I have a PhD in Hardware Engineering. My research in Luca Benini’s group at the Integrated Systems Laboratory focused on energy-efficient Computer Architectures and High-Performance Computing. My contributions include:

• Optimized Deep Neural Network training, improving energy/area efficiency by 3x compared to GPUs by developing a 32 bit float streaming processor that operates directly on memory. (Paper, Paper)

• Improved CPU throughput and resource utilization for single-issue in-order processors, achieving 3x performance and 2x energy efficiency gains by allowing instructions to implicitly encode loads/stores. (Paper)

• Co-authored and formally verified a RISC-V core, and doubled its peak performance by allowing integer and float pipelines to operate in parallel in a pseudo-dual-issue mode. (Paper)

• Developed a novel intermediate representation for Hardware Description Languages. (Paper)

• Designed, manufactured, and tested 6 ASICs in 22nm and 65nm technology nodes.

During my Master Thesis I have developed a generator for Standard Cell Memories. This involved designing and optimizing Custom Cell Layouts, transistor-level simulations in Spice, as well as Standard Cell Characterization. My work reduced memory access energy by 61% and area by 20%.

ABB is a technology leader that is driving the digital transformation of industries. With a history of innovation spanning more than 130 years, the company focuses on Electrification, Industrial Automation, Motion, and Robotics & Discrete Automation. It operates in more than 100 countries with about 147,000 employees.

During my delightful internship at ABB, I contributed to introducing Ethernet into electrical substation infrastructure. This involved Low-Level System Programming on commercial and open-source Real-Time Operating Systems, implementing commercial network protocols, and Linux Kernel Driver Development for custom networking hardware.