Fabian Schuiki

Hardware Engineer, Compiler Enthusiast, PhD Student

About Me

Hi, my name’s Fabian and I’m a Hardware Engineering PhD student.

ETH Zürich and Imperial College London are my almae matres.

I research energy-efficient Computer Architectures based on the RISC-V ISA by leveraging clever instruction set extensions and new memory architectures. Throughout my PhD, I have worked on various ASICs including RTL design, verification, synthesis, place & route, DRC fixing, and testing of the manufactured silicon on an industry-grade ASIC tester.

LLHD, Moore, and Bender are my flagship side projects.

I am most skilled in C/C++, Python, and SystemVerilog. During night hours I enjoy coding in Rust.


A foundation for building hardware design tools.

The Low Level Hardware Description language is an intermediate representation for digital circuit descriptions, together with an accompanying simulator and SystemVerilog/VHDL compiler.

LLHD separates input languages from EDA tools such as simulators, synthesizers, and placers/routers. This makes writing such tools easier, allows for more rich and complex HDLs, and does not require vendors to agree upon the implementation of a language.

See the LLHD talk and the PLDI paper.

A hardware compiler based on LLHD.

Moore is the HDL compiler accompanying the LLHD project. It implements the SystemVerilog and VHDL languages, and compiles them to LLHD IR. Developing a compiler for these languages, especially SystemVerilog, is extremely challenging due to their highly under-developed type systems, vast amount of syntactic legacy, and vague language standards. Moore tackles this via careful parser implementation, a modern query-based compiler architecture, and by integrating into efforts such as SymbiFlow/sv-tests.

Try the compiler online at llhd.io. See the LLHD talk.

A dependency management tool for hardware projects.

Bender is the dependency management tool that drives IP development and many ASIC tapeouts at the Integrated Systems Laboratory. Heavily inspired by Rust’s cargo, it implements fully decentralized dependency resolution and offers commands to generate compilation and analysis scripts for common ASIC and FPGA EDA tools.

A key challenge in supporting ASIC tapeouts is the necessity to provide reproducible builds at all costs, and catering to the hectic nature of last-minute global fixes to the code base. Bender tackles this problem through strict lock files, vendorization, and a hands-off approach to dependency checkouts.

See the Bender talk.



PLDI 2020

June 2020

I presented our paper submission “LLHD: A Multi-level Intermediate Representation for Hardware Description Languages” at the 41st ACM SIGPLAN Conference on Programming Language Design and Implementation (PLDI 2020).



MLIR Open Design Meeting

April 2020

At a recent MLIR Open Design Meeting I gave a talk on LLHD, a step towards an open ASIC design flow that fully supports existing Hardware Description Languages.

Slides Recording

PULP Overview

HotChips 31 at Stanford

August 2019

During the RISC-V tutorial session of the HotChips conference at Stanford University, I gave an overview of the PULP platform and our experience in developing RISC-V-based processors and platforms.

Slides Recording


Week of Open Source Hardware at ETH Zürich

June 2019

During the Week of Open Source Hardware, which was collocated with the RISC-V Summit at ETH, I gave a talk on Bender, the dependency management tool that drives many of our ASIC tapeouts.

Slides Recording



22nm (Globalfoundries)



Technology demonstrator designed by me and two fellow PhD colleagues, in collaboration with Globalfoundries.

Baikonur features three eight-core Snitch clusters, alongside two Ariane cores, and a custom purely-digital DDR link. It contains a total of 24 Snitch cores with 64-bit FPUs, which together with the Xssr and Xfrep extensions are capable of delivering up to 48 Gflop/s (float64) 96 Gflop/s (float32) each cycle.


22nm (Globalfoundries)



Technology demonstrator designed by me and two fellow PhD colleagues, in collaboration with Globalfoundries.

Kosmodrom features two 64-bit Ariane RISC-V cores (RV64GC) and an NTX cluster for ultra-energy-efficient training of Deep Neural Networks. The Ariane cores are implemented in two different standard cell flavours targeting different operating points. The NTX cluster contains a RISC-V core paired with 8 NTX units for 32-bit floating-point workloads.


22nm (Globalfoundries)



Fine-grained power gating demonstrator designed by me and fellow PhD colleagues and students.

Thestral features a total of 10 Snitch cores. One core serves as the system governor, one as the DMA controller, and the remaining 8 have individually power-gated 64-bit FPU and separate Integer Processing Units attached. The goal of this chip is to showcase that fine-grained power gating for functional units is feasible.


65nm (UMC)



Research chip designed by me and a fellow PhD colleague.

Billywig is a first implementation of a novel breed of processing systems, featuring 4 ultra-small Snitch cores (RV32IMAFD) paired with a large 64-bit FPU capable of vectorized 32-bit operations. The Xssr and Xfrep extensions allow the tiny core to operate in pseudo-dual-issue mode and achieve extreme energy efficiency.


65nm (UMC)



Designed by me and a fellow bachelor student.

Hecate is one out of a series of four student chips investigating techniques for sharing FPUs among processor cores. It features 4 OR10N OpenRISC cores, 2 FPUs, and a custom round-robin arbitrated sharing interconnect for the FPUs.


65nm (UMC)



Designed by four bachelor students under my supervision.

Xavier is geared towards acquisition of EEG signals and features a 32-bit RI5CY core (RV32ICMF), 8 SPI ports to attach ADCs, integrated filtering capabilities, and a hardware accelerator for Quantized Neural Networks.


65nm (UMC)



Designed by four bachelor students under my supervision.

Scarabaeus features a 64-bit Ariane RISC-V core (RV64GC), a custom DMA capable of multi-dimensional tensor transfers, and a custom HyperBus peripheral controller for interfacing with a Cypress HyperRAM.



ETH Zürich


PhD Student

November 2016 - Present

Master Thesis

February 2016 - August 2016

Established in 1854 with the stated mission to educate engineers and scientists, the school focuses exclusively on science, technology, engineering, and mathematics. More than twenty Nobel laureates, including Albert Einstein, have either studied at ETH or were awarded the Nobel Prize for their work achieved at ETH.

At present I am a PhD Student in Luca Benini’s group at the Integrated Systems Laboratory. My research focuses on energy-efficient Computer Architectures and High-Performance Computing. My contributions include:

  • Optimized Deep Neural Network training, improving energy/area efficiency by 3x compared to GPUs by developing a 32 bit float streaming processor that operates directly on memory. (Paper, Paper)

  • Improved CPU throughput and resource utilization for single-issue in-order processors, achieving 3x performance and 2x energy efficiency gains by allowing instructions to implicitly encode loads/stores. (Paper)

  • Co-authored and formally verified a RISC-V core, and doubled its peak performance by allowing integer and float pipelines to operate in parallel in a pseudo-dual-issue mode. (Paper)

  • Developed a novel intermediate representation for Hardware Description Languages. (Paper)

  • Designed, manufactured, and tested 6 ASICs in 22nm and 65nm technology nodes.

During my Master Thesis I have developed a generator for Standard Cell Memories. This involved designing and optimizing Custom Cell Layouts, transistor-level simulations in Spice, as well as Standard Cell Characterization. My work reduced memory access energy by 61% and area by 20%.



Corporate Research Intern

August 2013 - February 2014

ABB is a technology leader that is driving the digital transformation of industries. With a history of innovation spanning more than 130 years, the company focuses on Electrification, Industrial Automation, Motion, and Robotics & Discrete Automation. It operates in more than 100 countries with about 147,000 employees.

During my delightful intership at ABB, I contributed to introducing Ethernet into electrical substation infrastructure. This involved Low-Level System Programming on commercial and open-source Real-Time Operating Systems, implementing commercial network protocols, and Linux Kernel Driver Development for custom networking hardware.


ETH Zürich


MSc Electrical Engineering

September 2014 - November 2016

BSc Electrical Engineering

September 2010 - October 2014

Established in 1854 with the stated mission to educate engineers and scientists, the school focuses exclusively on science, technology, engineering, and mathematics. More than twenty Nobel laureates, including Albert Einstein, have either studied at ETH or were awarded the Nobel Prize for their work achieved at ETH.

During my time at ETH I learned most of my key skills such as team work, precision, and working to tight deadlines. The school taught me a thorough knowledge in Computer Architecture, Digital Circuits, Semiconductors, Communication Networks, and Network Security.

During my free time I taught myself complementary skills in Software Engineering and Compiler Design.

Imperial College London


BSc Electrical Engineering (Exchange Year)

October 2012 - June 2013

Established in 1907 by Royal Charter, the college focuses exclusively on science, technology, medicine and business. Imperial is among the top ten universities in the world, home to fourteen Nobel Laureates, three Field Medalists, and one Turing Award winner.

I have spent one year of my BSc education at Imperial College London in an exchange program. At Imperial I have learned essential engineering skills in Communication and Digital Circuits, as well as know-how in Project Management and Entrepreneurship at the Imperial Business School.